Two - Dimensional Rank Order Filter

a trademark of IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Summary This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm. The design is parameterizable for input/output precision, color standards, filter kernel size, maximum horizontal resolution, and implementation options. The rank to be selected can be modified dynamically, and the actual horizontal resolution is picked up automatically from the input synchronization signals. The design has a fully synchronous interface through the ce, clk, and rst ports.